In complementary metal oxide semiconductor (CMOS) technology a P channel insulated gate field effect transistor IGFET is in series with an N channel IGFET between a positive and a negative power supply terminal so that one of the two transistors is always off in a static condition to prevent current from flowing between the two power supply terminals in the static condition. Being able to detect a transistor transistor logic (TTL) output while keeping one of the P and N channel IGFETs off over the entire TTL output range is desirable in order to minimize power consumption. To conserve power is a typical reason for using CMOS. Because a TTL output can be as low as 2.0 volts for a logic "1", there is difficulty ensuring the P channel IGFET is off while contemporaneously ensuring the N channel IGFET is on.
There are CMOS circuits which operate at different logic levels which are interfaced in a manner so that one of the N and P channel transistors is off. In such a case one set of logic circuits operates at a lower power supply voltage than that of another set of circuits, with the lower power supply voltage set of circuits providing an output which must be interfaced with the other set of circuits. A pair of inverters are coupled to a pair of cross-coupled amplifiers. The pair of inverters operate at the lower power supply voltage and provide an output which is coupled to the pair of cross-coupled amplifiers which operate at the higher power supply voltage. A key aspect of the operation is that each set of logic circuits provide signals which are rail to rail, i.e., a logic "1" is provided at or very near the positive power supply voltage, and a logic "0" is provided at or very near the negative power supply voltage.
In TTL circuits, however, that is not the case. Because a TTL logic "1" output can be as low as 2.0 volts with a 5 volt power supply, the TTL logic is not directly analogous to the lower power supply set of CMOS circuits.